We design, implement, and deploy post-quantum secure systems.

  • The team investigates post-quantum secure computing systems and cryptosystems, examines their security vulnerabilities, advances algorithmic modifications for efficient hardware implementations, and performs cryptanalysis of these systems.

  • Post-Quantum Cryptography

  • Post-Quantum Hardware Library

  • Lattice-Based Cryptography

  • Code-Based Cryptography

  • Cryptographic Agility

  • Homomorphic Encryption Hardware

  • Zero Knowledge Proof

  • Post-Quantum Transition

  • Post-Quantum Cryptosystems Training

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Research, Development, and Training Portfolio

Algorithms Design

Code-based cryptosystems are still quantum resistant. We advance a new variant of the McEliece cryptosystem that takes advantage of non-binary Orthogonal Latin Square Code to achieve much lower complexity and key size.

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High-Performance Designs

A set of FPGA-based post-quantum cryptographic primitives (PQCPs) consisting of four frequently used security components, i.e., public key cryptosystem (PKC), key exchange (KEX), oblivious transfer (OT), and zero-knowledge proof (ZKP).

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Flexible Hardware Library

An open-source, hardware library with a focus on accelerating the arithmetic operations involved in Ring Learning with Error (RLWE)-based algorithms. Library components include RNS, CRT, NTT-based polynomial multiplication, etc.

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Homomorphic Encryption

We introduce new HE candidate architecture - Homomorphic-Encryption Enabled RISC-V (HERISCV) Processor which offers an order of magnitude improvement for a lattice cryptography processor with configurable parameters.

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Noise Sampling Designs

Small error sampling - we provide different noise samplers with the goal of providing concrete recommendations for future use and adoption in various cryptosystems based on sampling efficiency, hardware cost, and throughput.

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Low-Power Hardware Design

A key challange for PQC cryptosystems is their power consumption. We explore improvements that can enable their effective implementation in low-power portable/IoT devices.

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Proven QPC Hardware Design Flow

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Foundations of Quantum Resistant Cryptography

Following the NIST (National Institute of Standards and Technology) PQC proposal submissions and rounds, we have been investigating the mathematical foundations of the algorithms, real-time implementation, hardware architecture, open problems, attack vectors, and crypto-agility.

We have been examining their performance, parallelism, security under worst-case intractability assumptions, memory utilization, and latency. Our algorithmic and system work includes lightweight lattice-based cryptography, ultra-low latency, and seamless integration with the existing infrastructure.

Algorithm Design

Open-Source Hardware Implementation of PQC Primitives

We introduce a set of FPGA-based post-quantum cryptographic (PQC) primitives for the frequently used security protocols. This hardware tool has (1) FPGA-tailored implementations, (2) algorithmic optimizations to reduce area and latency costs without compromising security, and (3) open-sourcing the synthesizable and fully verifiable code. The RTL code base is fully parameterizable with an efficient, n-point Number-Theoretic Transform (NTT) module for fast polynomial multiplications.

Hardware Designs

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Privacy-Perserving Computing Solutions

The rise of connected and sensor-based devices have led to cloud computing being used as a commodity technology service.

One of the key persistent challenge with cloud-based computation is data privacy. Sensitive data is stored and computed over the cloud, which at most times, is a shared resource. Currently there are more than 2,500 cloud vulnerabilities - a 150% increase just in the last five years.

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Next-Generation Cryptosystems Design

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